1. Field of the Invention
The present invention relates to decoder/driver circuits for semiconductor memories, and more particularly to a NOR/NAND two-stage circuit that can be used as a word line decoder/driver in a CMOS random access memory.
2. Description of the Prior Art
In U.S. Pat. No. 4,063,118 issued Dec. 13, 1977 to Nishimura, entitled MIS DECODER PROVIDING NON-FLOATING OUTPUTS WITH SHORT ACCESS TIME describes a structure where, in a multiplicity of NAND decoders, each comprises a dynamic ratioless circuit including a capacitor to be charged in response to a precharge pulse, an MOS logic circuit for discharging the capacitor by an address pulse in the non-selection mode, and first and second MOSFETs connected in series between a clock pulse terminal and ground. The MOSFET conducts in response to the terminal voltage of the capacitor to transmit a clock pulse from its drain and supplies an output to a word line. The terminal voltage of the capacitor in one decoder is applied to the gate of the second MOSFET of another decoder and the word line output of the other decoder is grounded even during the discharging period of the capacitor in the non-selection mode of the other decoder, enabling a synchronous supply of the address and the clock pulses.
In U.S. Pat. No. 4,344,005 issued Aug. 10, 1982 to Stewart, entitled POWER GATED DECODING describes a decoder in which the decoding of N input variables to produce 2.sup.N unique outputs is carried out in steps, and in which some of the signals to be decoded also function to power part of the decoding circuitry. First, X of the N variables are decoded separately, as a group, to produce 2.sup.X unique outputs while the remaining N-X variables are also separately decoded, as a group to produce 2.sup.(N-X) unique outputs, where N and X are positive integers and X is less than N. Then, the outputs of the two groups are logically combined by means of 2.sup.N decoding buffer gates to produce 2.sup.N unique outputs. Each one of the 2.sup.X unique outputs is applied to the signal input terminals of 2.sup.(N-X) different ones of the 2.sup.N buffer gates and each one of the 2.sup.(N-X) unique outputs is used to power 2.sup.X different ones of the 2.sup.N buffer gates to produce 2.sup.N unique outputs of the N input variables, at the outputs of the buffer gates.
U.S. Pat. No. 4,514,829 issued Apr. 30, 1985 to Chao, entitled WORD LINE DECODER AND DRIVER CIRCUITS FOR HIGH DENSITY SEMICONDUCTOR MEMORY describes word line CMOS decoder and driver circuits for semiconductor memories wherein the pitch of the decoder is twice that of the word line, the number of decoders required is reduced by a half, and the word line selection pulse can be applied prior to word line selection. The decoder and driver circuits include a transistor clock load device having its gate electrode driven by a decoder clock pulse or address pulse and a plurality of decoder address switch devices having their gate electrodes driven, respectively, by a plurality of address signals. The clock load device and the address switch devices are connected to a common node at the input to an inverter stage.
U.S. Pat. No. 4,618,784 issued Oct. 21, 1986 to Chappell et al, entitled HIGH-PERFORMANCE, HIGH-DENSITY CMOS DECODER/DRIVER CIRCUIT, describes a decoder/driver circuit for a semiconductor memory having A1 to AN (true) and A1 to AN (complement) address lines for receiving A1 to AN address bit signals thereon from internal address buffers. The decoder/driver circuit includes a NOR decoder means having a plurality of transistor switching devices connected to A1 to AN-1 or A1 to AN-1 of the true and complement address lines for the AN to AN-1 address bits for producing a high or low level signal on a decoder output node depending on the address bits state. The decoder/driver circuit further includes a selection means having a plurality of transistor devices connected to the output node of the decoder to produce a first selection signal when the decoder output node and the AN line is high and a second selection signal when the decoder output node and the AN line is high. A driver circuit is connected to the selection means and is responsive to the output signal of the NOR decoder circuit and the first selection signal to provide an output signal on a first memory word line and is further responsive to the output signal of the NOR decoder circuit and the second selection signal to provide an output signal on a second memory word line.
A variety of decoder circuits for semiconductor memories are available in the art.
In U.S. Pat. No. 4,309,629 issued Jan. 5, 1982 to Kamuro, entitled MOS TRANSISTOR DECODER CIRCUIT, an MOS transistor decoder circuit is disclosed including a plurality of MOS transistors and at least one load element. At least one additional MOS transistor connected to the plurality of MOS transistors and the load element for selecting either of two output terminals for the plurality of MOS transistors, through which decoded output signals are developed. The two additional MOS transistors connected to the two output terminals have normal and complement bit signals, respectively.
In U.S. Pat. No. 4,264,828 issued Apr. 28, 1981 to Perlegos et al, entitled MOS STATIC DECODING CIRCUIT, a metal-oxide-semiconductor static decoding circuit for selecting an addressed line in a high density memory array, or the like, is disclosed. The circuit is laid-out along array lines where the lines have a given pitch. Three levels of decoding are employed. The highest level permits the pulling-up of a common node in the second level decoder. The third level of decoding selects one of a plurality of array lines coupled to this node. Zero threshold voltage MOS devices are employed for coupling the first and third decoders to the second decoder.
In U.S. Pat. No. 4,259,731 issued Mar. 31, 1981 to Moench, entitled QUIET ROW SELECTION CIRCUITRY, there is provided a quiet row select circuit for holding unselected word lines or row select lines in a memory array at a predetermined voltage potential. Transistors are used to couple each row select line to the predetermined voltage potential. The adjacent row select lines of at least one of the adjacent select lines is always coupled to the predetermined voltage when in an unselected state. A transistor is also used to couple each of the adjacent row select lines together and this transistor is enabled whenever the adjacent row select lines are non-selected so that both row select lines are coupled together to the predetermined voltage level.
In another reference of Moench, U.S. Pat. No. 4,200,917 issued Apr. 29, 1980, entitled QUIET COLUMN DECODER, a decoder is provided for semiconductor memory systems which prevents glitches from being coupled into the silicon substrate during the period of time that the sense amplifiers are sensing data on the bit sense lines. The quiet column decoder has double clock NOR gates which allows the address lines to be continuous non-multiplexed lines. The double clocked NOR gate has two transistors for precharging a first and a second node within the NOR gate. Another transistor is coupled between the second node and a voltage reference terminal to serve as an enabling device for the NOR gate. The first node of the NOR gate serves as an output for the column decoder.
In U.S. Pat. No. 4,429,374 issued Jan. 31, 1984 to Tanimura, entitled MEMORY ARRAY ADDRESSING, an address decoder for one memory axis is disclosed which comprises NAND circuits while the address decoder for the other axis comprises NOR circuits. A semiconductor memory circuit device comprises at least first and second decoder circuits. The first decoder circuit is so constructed as to receive at least partial address signals among address signals of a plurality of bits and to provide decoded signals of the partial address signals as intermediate signals. The second decoder circuit is so constructed as to receive the intermediate signals, to thereby provide signals for selecting from among a plurality of memory circuits a memory circuit determined by the address signals of the plurality of bits.
A publication entitled "CMOS Decoder Circuit" by L. M. Terman, at page 2135 of Vol. 25, No. 4 Sept. 1982 of the IBM Technical Disclosure Bulletin relates to improvements in CMOS decoder circuits, and particularly to a decoder circuit which does not dissipate DC power. The decoder is followed with two branches with CMOS drivers for word lines.
In Vol. 18, No. 12, May 1976 of the IBM Technical Disclosure Bulletin, G. H. Parikh in a publication entitled "High Speed FET Decoder" on page 3955 describes a field-effect transistor decoder circuit which allows improved speed of decoding FET random-access memories, by reducing the capacitance required to be discharged in an unselected decoder.
The speed is further increased by reducing the capacitance of the nodes to be discharged wherein isolation transistor devices are provided to isolate the capacitance on word line voltage nodes to allow bootstrapping to occur if a node has not been discharged.
Other related prior art includes the following references:
U.S. Pat. No. 4,194,130 to Moench issued Mar. 18, 1980, entitled DIGITAL PREDECODING SYSTEM;
U.S Pat. No. 4,433,257 to Kinoshita issued Feb. 21, 1984, entitled VOLTAGE SUPPLY FOR OPERATING A PLURALITY OF CHANGING TRANSISTORS IN A MANNER WHICH REDUCES MINORITY CARRIER DISRUPTION OF ADJACENT MEMORY CELLS;
U.S. Pat. No. 4,156,938 to Proebsting et al issued May 29, 1979, entitled MOSFET MEMORY CHIP WITH SINGLE DECODER AND BI-LEVEL INTERCONNECT LINES.